pacino pipeline (simplified)
Swipe to see the full pipeline
Some interesting lessons learned so far, with links to the relevant posts and IA tasks.
Out-of-order RVA23S64 RISC-V processor: an 8-issue OOO design targeting competitive SPECint2006 performance. RTL, design decisions, and AI co-design methodology published in the open.
Finds recurring LLM prose constructions in markdown or plain text, so a human can decide what to cut. Used on every uarchlabs blog post.
Cache RTL and C++ model generator. The released example is a 1 MB 4-way cache with tree-PLRU, directed tests and a functional model.
What is uarchlabs?
uarchlabs is a research-first open source lab exploring how large language models can accelerate microarchitecture design. We share synthesizable RTL alongside the AI-assisted methodology that produced it: prompts, evaluation loops, and design rationale included. Why we started.
Who is it for?
Chip architects, hardware researchers, and curious engineers who want to understand both the what and the how of AI-driven hardware design. Whether you want to study the methods, extend the RTL, or contribute, start with the docs.
Open RTL
Every design is released as synthesizable RTL under a permissive license. Inspect it, fork it, tape it out.
AI co-design methods
We document the full AI-assisted workflow, not just the output.
Community first
Issues, discussions, and design decisions happen in public on GitHub.