uarchlabs builds and publishes high-performance processors.
Our first project is Pacino — an 8-issue out-of-order RISC-V processor designed for competitive SPEC performance.
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Every design is released as synthesizable RTL under a permissive license — inspect, fork, and tape out.
We document the full AI-assisted workflow — prompts, iteration loops, evaluation harnesses — not just the output.
Built in the open from day one. Issues, discussions, and design decisions happen in public on GitHub.
uarchlabs is a research-first open source lab exploring how large language models can accelerate microarchitecture design. We share synthesizable RTL alongside the AI-assisted methodology that produced it — prompts, evaluation loops, and design rationale included.
Chip architects, hardware researchers, and curious engineers who want to understand both the what and the how of AI-driven hardware design. Whether you want to study the methods, extend the RTL, or contribute — start with the docs.
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